1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the device.
2. Description of Related Art
Hitherto, as one kind of nonvolatile semiconductor memory device, an ultraviolet erasable EPROM (Erasable and Programmable Read Only Memory) has been known which has a capacity that is gradually becoming greater. However, when the capacity of an EPROM increases, defective bits can occur due to problems of manufacturing which, results in the deterioration in the yield of EPROMs. Therefore, for EPROMs which have a large capacity, generally, redundant bits so as to compensate for defective bits and a redundant bit programming circuit so as to select the redundant bits are provided in the memory device, and the defective bits are replaced by redundant bits to compensate for the defective bits. In this case, the redundant bit programming circuit is ordinarily constructed with EPROM memory transistors.
However, when data in the EPROM itself is erased, ultraviolet rays are also irradiated onto the redundant bit programming circuit. Therefore, to prevent the data written in the redundant bit programming circuit from being erased by the irradiation of the ultraviolet rays, it is necessary to take countermeasures so as not to irradiate the ultraviolet rays onto the EPROM memory transistors of the redundant bit programming circuit.
Hitherto, as a countermeasure for such purpose, in general, the upper portion of the EPROM memory transistors for the redundant bit programming circuit has been covered by a first layer of aluminum (Al) film which form wirings so as to thereby shield the upper portion from light.
However, even when the EPROM memory transistors for the redundant bit programming circuit are shielded from light by a first layer of Al film as mentioned above, the following problems still exist. First, since the space between the first layer of Al film and a semiconductor substrate is fairly large, the ultraviolet rays which entered from the portions which are not shielded from the light by the Al film cause a multiple reflection between the surface of the semiconductor substrate and the lower surface of the Al film, so that the ultraviolet rays easily enter the EPROM memory transistors under the Al film. Second, it is necessary to form Al wirings for the source region, drain region, and control gate, and since it is necessary to maintain certain distances between the Al wirings, when the ultraviolet rays are irradiated, the ultraviolet rays enter from the regions between the Al wirings. To prevent this, it is necessary to change the shapes of the source region, drain region, and control gate, so that the area for the EPROM memory transistors for the redundant bit programming circuit becomes large. Moreover, in spite of such a large area structure, it is difficult to sufficiently suppress the irradiation of the ultraviolet rays to the EPROM memory transistors for the redundant bit programming circuit.
On the other hand, as disclosed in Japanese Patent Laid-Open Publication No. Hei 2-79477, the applicant of the present invention has proposed a nonvolatile semiconductor memory device and a manufacturing method in which a phospho-silicate glass (PSG) film containing phosphorus of 1 to 8 weight %, a silicon nitride (Si.sub.3 N.sub.4) film, and an arseno-silicate glass (AsSG) film or a boro-phospho-silicate glass (BPSG) film are sequentially formed on a floating gate, and by using such a structure, the data retention characteristics of an EPROM or an EEPROM (Electrically Erasable and Programmable Read Only Memory) can be improved.
As mentioned above, by using the three layer structure comprising PSG/Si.sub.3 N.sub.4 /AsSG or PSG/Si.sub.3 N.sub.4 /BPSG as the interlayer insulating film, the data retention characteristics can be improved. However, when the integration density increases and contact holes become small, the following problems result. These problems will be described in detail hereinbelow with reference to FIGS. 1A and 1B.
FIGS. 1A and 1B show a conventional manufacturing method of an EPROM.
As shown in FIG. 1A, according to the conventional manufacturing method of an EPROM, a field insulating film 102, a gate insulating film 103, a floating gate FG", a control gate CG", insulating films 104 and 105, and a source region 106 and a drain region 107 of, for instance, an N.sup.+ -type are formed on a p-type silicon (Si) substrate 101, for example. Then a PSG film 108, an Si.sub.3 N.sub.4 film 109, and an AsSG film 110 are formed as interlayer insulating films on the whole surface. As already mentioned above, a BPSG film can be also used in place of the AsSG film 110.
Then, a resist pattern (not shown) in which portions corresponding to contact holes to be formed is formed on the AsSG film 110. Then the AsSG film 110, Si.sub.3 N.sub.4 film 109, PSG film 108, and gate insulating film 103 are sequentially etched by using the resist pattern as mask. Thus, as shown in FIG. 1B, contact holes C.sub.1 ' and C.sub.2 ' are formed. Then the resist pattern is removed.
A reflow of the AsSG film 110 is then executed by performing a thermal treatment. Thus, the shoulder portions of the contact holes C.sub.1 ' and C.sub.2 ' are set into a smooth round shape as shown by alternate long and short dash lines in FIG. 1B. Then, an Al film and An Al-Si alloy film to form wirings are formed by a sputtering method or an evaporation method. Prior to this as a pre-processing, light etching is first executed by using an etchant of the hydrofluoroic acid (HF) system. Then, after the Al film or Al-Si alloy film has been formed, this film is patterned into a predetermined shape by etching, thereby forming wirings (not shown) which respectively come into contact with the source region 106 and drain region 107 through the contact holes C.sub.1 ' and C.sub.2 '.
However, during the above described light etching, the PSG film 108 which is exposed on the inside of the contact holes C.sub.1 ' and C.sub.2 ' is also etched into a shape as shown by broken lines in FIG. 1B. Thus, there is a problem such that the shapes of the contact holes C.sub.1 ' and C.sub.2 ' after completion of the light etching deteriorate and there is the danger that the shape deterioration results in a cause of a defective contact or the like.
On the other hand, in the EPROM and EEPROM, hitherto both the floating gate and the control gate are formed with an N.sup.+ -type polycrystalline Si film. In recent years, in accordance with the requirements for realization of large capacity and high speed of the EPROM and EEPROM, as the material of the control gate, it has been necessary to use a low resistivity material such as polycide film in which a silicide film of a refractory metal such as tungsten silicide (WSi.sub.2) film, molybdenum silicide (MoSi.sub.2) film, or the like is formed on an N.sup.+ -type polycrystalline Si film, refractory metal film, or the like.
When a thermal oxide film of good quality is formed on the side walls around the floating gate, good data retention characteristics are obtained. However, for this purpose, it is desired to execute the thermal oxidation at a temperature of 1000.degree. C. or higher.
In the EPROM, the EEPROM, or the like having a high integration density, there is generally used a so-called double self-alignment method in which a floating gate and a control gate are formed by simultaneously patterning using one mask. According to the double self-alignment method, the side surfaces of the floating gate in the direction of channel length (direction connecting a source region and a drain region) of a memory transistor are formed so as to be self-aligned with the control gate. Therefore, in the case where the control gate was formed by, for instance, a polycide film, upon thermal oxidation to form an oxide film on the side walls of the floating gate, a refractory metal silicide film such as a WSi.sub.2 film or the like is exposed. However, in this state, if the thermal oxidation of a high temperature of, e.g., 1000.degree. C. or higher is executed, there is a large possibility such that refractory metal atoms such as tungsten (W) or the like cause an out-diffusion from the refractory metal silicide film. The refractory metal atoms which caused the out-diffusion are taken into an Si substrate, a thermal oxide film is formed around the floating gate, a thermal oxide film is formed on the Si substrate, and the like, so that a trap level or the like is formed. Such refractory metal atoms easily become a cause of leakage for a cause of breakdown of the oxide film.
For the improvement of the data retention characteristics, the present applicant has proposed in Japanese Patent Laid-Open Publication No. Hei 2-31466 a method whereby by executing a thermal oxidation in a state in which a control gate and a floating gate are covered by a semiconductor layer such as a polycrystalline Si film or the like, a semiconductor oxide film of good film quality is formed on the side walls of the floating gate.